1. Field of the Invention
The invention relates to a serial interface cache controller, and more particularly to a cache controller capable of decreasing the data quantity read from an external memory so that a serial interface bandwidth of a cache memory may be reduced.
2. Related Art
FIG. 1 shows the architecture of a typical micro-control system 10 for accessing data from an external memory in parallel. Referring to FIG. 1, the micro-control system 10 includes a micro-controller 11 connected to an external memory 12. The external memory 12 may be a flash memory or any other memory capable of storing data. The micro-control system 10 accesses the data in the external memory 12 in parallel. The micro-control system 10 needs to have many pads for an address bus, a data bus and the like. Consequently, the micro-control system 10 has the higher access speed, and the chip area has to be enlarged for the pads so that the low-cost requirement cannot be satisfied.
FIG. 2 shows the architecture of a typical micro-control system 20 for serially accessing data from an external memory. Referring to FIG. 2, the micro-control system 20 includes a micro-controller 11, an internal memory 21 and a serial interface read controller 22. The micro-control system 20 is connected to an external memory 23. Because the micro-control system 20 serially reads the data from the external memory 23, many pads may be saved, and the pad cost and the chip area may be reduced. Before the micro-control system 20 starts to operate, the serial interface read controller 22 has to download the whole program from the external memory 23 to the internal memory 21. Therefore, the capacity of the internal memory 21 has to be the same as that of the external memory 23. For example, the micro-controller with a 16-bit address bus may directly correspond to the memories ranging from 0000H to FFFFH, which are 64K bytes in total. Thus, if the external memory 23 has 64K bytes, the internal memory 21 may also have 64K bytes. Therefore, the micro-control system 20 needs not to provide a lot of pads, but the larger internal memory is needed. Because the internal memory usually needs the higher access speed, the static memory (SRAM) with the higher cost and the larger capacity still cannot satisfy the low-cost requirement.
Thus, if the cache technology is combined with the serial data reading, the pad cost and the internal static memory requirement of the micro-control system may be reduced. FIG. 3 shows a micro-control system 30 having the cache technology combined with the serial data reading. The micro-control system 30 includes a micro-controller 11, an internal cache memory 32, a cache controller 31 and a serial interface read controller 22. The micro-control system 30 is connected to an external memory 23. The cache controller 31 typically includes L rows of address tags for recording address blocks stored in the internal cache memory 32. Furthermore, each row of address tags includes M bits of block tags and represents the address block of T-byte data. For example, the cache controller 31 includes eight rows of address tags, wherein each said row of address tags includes 8 bits of block tags and represents the address block of 256-byte data.
When the micro-control system 30 starts to operate, the cache controller 31 compares the data of micro-controller read-out address outputted form the micro-controller 11 with the data stored in the block tags of the eight rows of address tags to judge whether the reading data has been stored in the internal cache memory 32. When the cache controller 31 makes sure that the data of the micro-controller read-out address has been stored in the internal cache memory 32 (the condition of hit), the cache controller 31 directly transfers the data from the internal cache memory 32 to the micro-controller 11. When the cache controller 31 makes sure that the data of the micro-controller read-out address is not stored in the internal cache memory 32 (the condition of miss), the serial interface read controller 22 downloads the 256-byte data (program code) from the external memory 23 to the internal cache memory 32. Thereafter, the cache controller 31 transfers the data needed to the micro-controller 11.
In the typical cache control method, the L rows of address tags are used to record the high-bit (MSB) address corresponding to the address of the internal cache memory. FIG. 4 shows the architecture of address tag rows in a conventional cache controller. For example, each row of address tags records 8 bits of high-bit address data, and the corresponding data quantity is 256 bytes. Therefore, if eight rows of address tags are used, the internal cache memory needs to have about 2048 bytes. However, when the data is not stored in the internal cache memory 32, 256 bytes of data have to be downloaded from the external memory 23 to the internal cache memory 32 at each time. Because the micro-controller 11 operates in a waiting state during the data downloading period, the performance or efficiency of the micro-control system 30 is influenced when the data quantity downloaded is too large. In addition, not all the data in the internal cache memory 32 will be read and utilize well. Therefore, it is desirable to provide an improved cache control method to mitigate and/or obviate aforementioned problems.